| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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9,040 pcs
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9040 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| SVHC Present |
The Altera EP1K30TI144-3 is a member of the ACEX 1K family of Programmable Logic Devices (PLDs). It provides a cost-efficient programmable architecture suitable for high-volume applications, including complex logic and memory functions.
This FPGA utilizes a look-up table (LUT) architecture combined with Enhanced Embedded Array Blocks (EABs). The LUT-based logic is optimized for data-path, register-intensive, mathematical, or digital signal processing (DSP) designs. EABs are capable of implementing RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions, with dual-port capability up to 16-bit width per EAB.
The EP1K30TI144-3 offers a density range of 10,000 to 100,000 typical gates and can support up to 49,152 RAM bits. It operates with a 2.5-V core voltage, making it suitable for low-cost, high-volume applications.
The device is supplied in a QFP package. Its architecture incorporates features necessary for implementing common gate array megafunctions and provides a high pin count for effective system component interfacing.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EP1K30TI144-3 FPGA offers 10,000 to 100,000 typical gates.
The EP1K30TI144-3 FPGA supports up to 49,152 RAM bits.
The EP1K30TI144-3 FPGA has a 2.5-V core voltage requirement.
The EP1K30TI144-3 FPGA is supplied in a QFP package.
Yes, the EP1K30TI144-3 supports dual-port capability with up to 16-bit width per embedded array block (EAB).
The Moisture Sensitivity Level (MSL) for the EP1K30TI144-3 is 1 Unlimited.