| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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25,829 pcs
|
25829 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
1,200 pcs
|
1200 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
270 pcs
|
270 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Tape & Reel |
The Altera EP1K100FI484-2N is part of the ACEX-1K family of Programmable Logic Devices (PLDs), offering system-on-a-programmable-chip (SOPC) integration. This FPGA provides a high density of up to 100,000 typical gates and supports up to 49,152 RAM bits. It features 4992 logic elements and 333 user I/O pins, making it suitable for high-volume applications.
System-level features include MultiVolt I/O pins that can interface with 2.5-V, 3.3-V, or 5.0-V devices, and low power consumption. The device offers bidirectional I/O performance up to 250 MHz. It is compliant with the PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz, and -1 speed grade devices are compliant for 5.0-V operation. The internal supply voltage is 2.5-V.
This device is housed in a 484-BBGA package and requires surface mounting. It operates within an extended temperature range of -40°C to 85°C. The ACEX-1K series is known for its cost-efficient programmable architecture and is designed for high-performance communications applications.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EP1K100FI484-2N has a typical gate count of 100,000.
The device features 4992 logic elements.
The EP1K100FI484-2N offers a total of 49,152 RAM bits.
It has a maximum of 333 user I/O pins.
The MultiVolt I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices.
The operating temperature range is -40°C to 85°C.
Yes, it is fully compliant with the PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz, and -1 speed grade devices are compliant for 5.0-V operation.