| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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6,027 pcs
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6027 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| SVHC Present |
The Altera EP1C6Q24017N is a member of the Cyclone field-programmable gate array family. It is built on a 1.5-V, 0.13-μm, all-layer copper SRAM process, providing densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM.
This FPGA supports features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface for DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, making it a cost-effective solution for data-path applications. The EP1C6Q24017N supports various I/O standards, including LVDS at data rates up to 640 Mbps, and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI).
Key features include up to 294,912 RAM bits, support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards, high-speed (640 Mbps) and low-speed (311 Mbps) LVDS I/O support, and 311-Mbps RSDS I/O support. It also includes up to two PLLs per device for clock multiplication and phase shifting.
The EP1C6Q24017N comes in a QFP package and operates at a 1.5V supply voltage. It is suitable for applications requiring flexible logic implementation and high-speed data processing.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EP1C6Q24017N has 20,060 logic elements.
The core operating voltage is 1.5V.
The EP1C6Q24017N is available in a QFP package.
It supports LVTTL, LVCMOS, SSTL-2, SSTL-3, LVDS, RSDS, and PCI.
The high-speed LVDS data rate is 640 Mbps.
Yes, it supports DDR SDRAM (133 MHz), FCRAM, and SDR SDRAM.
The device has up to two PLLs.