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38 pcs
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38 pcs | On Request | 1 | On Request | On Request | N/A | On Request | On Request |
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The Altera EP1810GM-45 is a member of the Classic EPLD family, designed for high-speed, low-power logic integration. Fabricated on advanced CMOS technology, this device utilizes sum-of-products logic and programmable registers.
Key technical specifications include a logic density of up to 900 usable gates, fast pin-to-pin logic delays as low as 10 ns, and counter frequencies reaching up to 100 MHz. The device is available in a CPGA68 package.
Programmable registers can be configured for D, T, SR, or JK flip-flop operation, or bypassed for combinatorial logic. Macrocell registers can be clocked by a global clock or any input/feedback path. The EP1810GM-45 also features a programmable security bit for design protection and is 100% generically tested for programming yield.
This FPGA is suitable for applications requiring efficient logic implementation with low power consumption and high-speed performance. Software design support is available through the Altera MAX+PLUS II development system.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.17 | $1.17 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EP1810GM-45 offers up to 900 usable gates.
The minimum pin-to-pin logic delay is 10 ns.
The counter frequency can be as high as 100 MHz.
The EP1810GM-45 is supplied in a CPGA68 package.
The EP1810GM-45 is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) is 1 Unlimited.
The EP1810GM-45 is REACH Unaffected.