| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
67 pcs
|
67 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| SVHC Present |
The Texas Instruments DS90CR484 is a 48-Bit Channel Link Deserializer designed for high-speed data transmission. It operates with input clock frequencies ranging from 33 MHz to 112 MHz, providing a substantial data throughput of up to 5.38 Gbits/sec.
This device converts LVDS data streams back into 48 bits of CMOS/TTL data. Key features include a +3.3V supply voltage, 5V tolerant input pins, and conformance to the ANSI/TIA/EIA-644-1995 LVDS standard. The design incorporates features like pre-emphasis to reduce cable loading effects and DC balance data transmission to minimize ISI distortion.
The DS90CR484 is available in a 100-lead TQFP package with a body size of 16 mm x 16 mm. Its flow-through pinout facilitates easier PCB design. The multiplexing of data lines significantly reduces cable size compared to traditional parallel buses.
This part is noted as 'NOT RECOMMENDED FOR NEW DESIGNS', suggesting that newer alternatives may be available for new projects.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The DS90CR484VJD operates with a +3.3V supply voltage.
The DS90CR484VJD is available in a TQFP (NEZ) 100 package.
The DS90CR484VJD offers a bandwidth of up to 5.38 Gbits/sec.
The input clock support for this device is 33 MHz to 112 MHz.
Yes, it conforms to the ANSI/TIA/EIA-644-1995 LVDS Standard.
It provides cable deskew of +/-1 LVDS Data Bit Time for clock rates up to 80 MHz.
Yes, the TxIN and Control Input Pins are 5V tolerant.