| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
426 pcs
|
426 pcs | On Request | 1 | On Request | On Request | 1319+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Access Time | |
| Bus Directional | |
| Current | |
| Data Rate | |
| Expansion Type | |
| FWFT Support | |
| Function | |
| Lead Style | |
| Memory Size | |
| Mounting Type | |
| Operating Temperature | |
| Programmable Flags Support | |
| Retransmit Capability | |
| Speed | |
| Supplier Device Package | |
| Voltage |
The Cypress Semiconductor CY7C421-20JXC is a 512 words by 9 bits wide asynchronous First-In First-Out (FIFO) buffer memory. It features a high speed of 50 MHz for both read and write operations, independent of depth and width. The device operates with a low power consumption of 35 mA typical.
Key specifications include a 20 ns maximum access time and a wide operating voltage range of 4.5 V to 5.5 V. It provides empty and full flags for overflow and underflow prevention, and supports retransmit functionality in standalone configurations. The CY7C421-20JXC is designed for expandable width and depth configurations.
This FIFO memory is available in a 32-PLCC (11.43x13.97mm) or 32-LCC (J-Lead) package, suitable for surface mounting. It operates within a temperature range of 0°C to 70°C. The device is pin-compatible and functionally equivalent to IDT7201 and AM7201.
It is fabricated using an advanced 0.65-micron P-well CMOS technology, offering TTL compatibility and high speed independent of depth and width. The CY7C421-20JXC is designed to prevent overflow and underflow with its provided flags.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.50 | $1.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
4.5 V to 5.5 V.
0°C to 70°C.
32-PLCC (11.43x13.97 mm) and 32-LCC (J-Lead).
20 ns.
50 MHz.
Asynchronous.
Yes, it supports retransmit capability.