| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
3,150 pcs
|
3150 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| Clock Frequency | |
| Configuration | |
| Halogen Free | |
| Industrial Grade | |
| Lead Style | |
| Mounting Type | |
| SVHC Present |
The Cypress Semiconductor CY7C2265KV18-550BZXI is a 36-Mbit synchronous Pipelined SRAM utilizing the QDR II+ architecture. This design provides separate independent read and write data ports, enabling concurrent transactions and eliminating data bus turnaround time.
Key features include a high-speed 550 MHz clock, supporting double data rate (DDR) interfaces for data transfer at 1100 MHz. It offers a 2.5 clock cycle read latency when DOFF is asserted HIGH, and a 1 clock cycle latency when DOFF is asserted LOW. The device supports both 1.5 V and 1.8 V I/O supplies and features HSTL inputs with variable drive HSTL output buffers.
This SRAM is configured as 1M x 36 bits and comes in a 165-ball FBGA package measuring 13 x 15 x 1.4 mm. It is suitable for applications requiring high bandwidth and efficient data access due to its burst architecture and independent port design.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.28 | $1.28 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The CY7C2265KV18-550BZXI has a clock speed of 550 MHz.
The read latency is 2.5 clock cycles when DOFF is asserted HIGH, and 1 clock cycle when DOFF is asserted LOW.
The CY7C2265KV18-550BZXI is configured as 1M x 36 bits.
The core voltage is 1.8 V, and it supports I/O voltages of 1.5 V and 1.8 V, with a range of 1.4 V to VDD.
The CY7C2265KV18-550BZXI is available in a 165-FBGA package.
The RoHS status is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) is 1 Unlimited.