| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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734 pcs
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734 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Technology |
The Infineon CY23S09SXC-1 is a low-cost, 3.3V zero delay buffer built using advanced 0.65μm CMOS technology. It is designed to efficiently distribute high-speed clocks, making it suitable for CPU and PCI bus frequencies.
This device features a single input that drives up to nine outputs, grouped as 4 + 4 + 1. It offers multiple low-skew outputs with an output-to-output skew of less than 250 ps and device-to-device skew of less than 700 ps. The zero input-to-output propagation delay and less than 200 ps cycle-to-cycle jitter ensure precise clock timing.
The CY23S09SXC-1 operates in the frequency range of 10 MHz to 133 MHz. It includes on-chip PLLs that lock to the reference input. The device supports a test mode to bypass the PLL for chip and system testing. When no rising edges are detected on the reference input, the PLL enters a power-down mode, significantly reducing current draw.
Available in a space-saving 16-pin SOIC package, the CY23S09SXC-1 is designed for surface mount applications. Its advanced features and reliable performance make it a strong choice for clock distribution in various electronic systems.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.88 | $1.88 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The operating frequency range is from 10 MHz to 133 MHz.
The output-to-output skew is less than 250 ps.
The device-to-device skew is less than 700 ps.
The cycle-to-cycle jitter is less than 200 ps.
The operating voltage is 3.3 V.
The CY23S09SXC-1 is available in a 16-pin SOIC package.