| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
17,500 pcs
|
17500 pcs | On Request | 1 | On Request | On Request | 07+ | On Request | On Request | |
|
128 pcs
|
128 pcs | On Request | 1 | On Request | On Request | 0376513Q | On Request | On Request | |
|
89 pcs
|
89 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| SVHC Present |
The Cypress Semiconductor CY2305SXC1 is a Zero Delay PLL Clock Buffer designed for clock distribution applications. It features a single-phase-locked loop architecture and supports input signals of LVCMOS and LVTTL types.
This component operates within a supply voltage range of 3V to 3.6V, with a maximum output frequency of 133.33 MHz. The operating temperature range is from 0 C to +70 C. The device is housed in a SOIC-8 package and is supplied in a tube.
Key electrical characteristics include 5 outputs and support for LVCMOS/LVTTL inputs. The device is suitable for applications requiring precise clock signal generation and distribution.
| Qty | Low | High |
|---|---|---|
| 1+ | $3.00 | $3.00 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The output frequency range is 10 MHz to 133.33 MHz.
The supply voltage range is 3 V to 3.6 V.
The operating temperature range is 0°C to +70°C.
The CY2305SXC1 is available in an SOIC-8 package.
The CY2305SXC1 has 5 outputs.
The CY2305SXC1 accepts LVCMOS and LVTTL input signals.