CY2304SXI-1

The CY2304SXI-1 from Cypress Semiconductor is a 3.3V Zero Delay Buffer engineered for distributing high-speed clocks in demanding applications like PCs, workstations, datacom, and telecom systems. It utilizes an on-chip phase-locked loop (PLL) to lock onto an input clock signal.

Key features include zero input-to-output propagation delay, adjustable by capacitive load on the FBK input. The device offers multiple low-skew outputs and operates across a frequency range of 10 MHz to 133 MHz. It exhibits a typical peak cycle-to-cycle jitter of 90 ps at 15 pF and 66 MHz. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is less than 200 ps.

This buffer is available in a space-saving 8-pin SOIC package, making it suitable for designs where board space is limited. It supports industrial temperature ranges and features a power-down state that reduces current draw to less than 25 μA when no rising edges are detected on the REF input.

The CY2304SXI-1 is part of the CY2304 family, offering different configurations for frequency division. This specific part, CY2304-1, provides reference frequencies on its outputs when the feedback loop does not include a counter.