| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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4,510 pcs
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4510 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
2,597 pcs
|
2597 pcs | On Request | 1 | On Request | On Request | 07+ | On Request | On Request |
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The CDCVF2510APW from Texas Instruments is a 3.3V Phase-Lock Loop (PLL) clock driver. It is engineered to precisely align clock signals in both frequency and phase, making it ideal for synchronous DRAM applications. The device features one clock input that is distributed to a bank of 10 low-skew, low-jitter LVTTL outputs.
Key electrical specifications include a core and output supply voltage of 3.3V, an operating frequency range from 20 MHz to 175 MHz, and an output skew of 100 ps. The additive RMS jitter is typically 70 fs. The device operates within a temperature range of 0°C to 85°C.
Designed for ease of use, the CDCVF2510APW includes on-chip series damping resistors, eliminating the need for external RC networks. It supports a power-down mode via auto frequency detection. The component is housed in a 24-TSSOP package and is suitable for surface mount applications.
Applications include DRAM systems, PLL-based clock distributors, and non-PLL clock buffers. Its design meets and exceeds the PC133 SDRAM Registered DIMM Specification Rev. 1.1 and is spread spectrum clock compatible.
| Qty | Low | High |
|---|---|---|
| 1+ | $3.32 | $3.32 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The operating voltage for the CDCVF2510APW is between 3V and 3.6V.
The CDCVF2510APW is supplied in a 24-TSSOP package.
The operating temperature range for the CDCVF2510APW is 0°C to 85°C.
Yes, the CDCVF2510APW is RoHS3 Compliant.
The CDCVF2510APW has 10 outputs.
The maximum operating frequency of the CDCVF2510APW is 175 MHz.
The output skew of the CDCVF2510APW is 100 ps.