| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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993 pcs
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993 pcs | On Request | 1 | On Request | On Request | 04+ | On Request | On Request |
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The CDCVF25081DR from Texas Instruments is a 3.3V phased-locked loop (PLL) clock driver designed for high-performance timing applications. This device features a 1:8 clock distribution ratio, providing 8 buffered LVTTL outputs from a single LVTTL input. It utilizes a PLL to precisely align the output clocks in both frequency and phase to the input clock signal, ensuring low additive jitter of typically 100 fs (RMS) and output skew of 150 ps.
The CDCVF25081DR operates over a supply voltage range of 3V to 3.6V and supports operating frequencies from 8 MHz to 200 MHz. It includes a power-down mode that automatically sets outputs to a low state when no input clock signal is present, reducing current consumption to less than 20 µA. The device also incorporates 25-Ω on-chip series damping resistors and input hysteresis for stable operation.
Packaged in a 16-pin SOIC (0.154", 3.90mm Width), the CDCVF25081DR is suitable for surface mount applications. It is characterized for an industrial operating temperature range of -40°C to 85°C. The device supports Spread Spectrum Clocking (SSC) compatibility.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.94 | $1.94 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The CDCVF25081DR operates with a supply voltage range of 3 V to 3.6 V.
The CDCVF25081DR provides 8 outputs.
The CDCVF25081DR supports a maximum operating frequency of 200 MHz.
The typical output skew for the CDCVF25081DR is 150 ps.
The operating temperature range for the CDCVF25081DR is -40°C to 85°C.
The CDCVF25081DR is available in a 16-SOIC package.