| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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300 pcs
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300 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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150 pcs
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150 pcs | On Request | 1 | On Request | On Request | 1419/ | On Request | On Request |
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| PLL | |
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The Texas Instruments CDC2509APWR is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It operates at 3.3V VCC and provides integrated series-damping resistors, making it suitable for driving point-to-point loads.
This device distributes one clock input to one bank of five outputs and one bank of four outputs, providing nine low-skew, low-jitter copies of the input clock. The output signal duty cycles are adjusted to 50 percent, independent of the input clock's duty cycle. Each bank of outputs can be enabled or disabled separately via control inputs.
The CDC2509APWR features on-chip series damping resistors and does not require an external RC network for its PLL loop filter, minimizing component count and board space. It is characterized for operation from 0°C to 70°C.
Packaged in a 24-TSSOP, the CDC2509APWR is designed for surface mount applications. Its key specifications include a maximum frequency of 100 MHz, an input/output type of LVTTL, and a clock ratio of 1:9.
The operating voltage for the CDC2509APWR is 3.3 V.
The CDC2509APWR is supplied in a 24-TSSOP package.
The CDC2509APWR operates between 0°C and 70°C.
The RoHS status is RoHS3 Compliant.
The frequency of the CDC2509APWR is 100 MHz.
The input voltage range for the CDC2509APWR is 3 V to 3.6 V.
Yes, the CDC2509APWR has PLL functionality with bypass.