| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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1,000 pcs
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1000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | 2026-06-29 21:33:16 | |
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25 pcs
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25 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name |
The CD54HCT175F3A from Texas Instruments is a high-speed CMOS logic integrated circuit featuring four D-type flip-flops. Each flip-flop has individual D inputs and complementary Q and Q\ outputs, along with common clock and asynchronous reset capabilities. This device utilizes silicon gate CMOS technology and is designed for TTL-compatible input logic.
Key electrical characteristics include a maximum clock frequency of 16 MHz, a maximum output current (IOL) of 4 mA, and a maximum output current (IOH) of -4 mA. The supply current is a maximum of 160 µA. Propagation delay (tpd) ranges from 10 to 50 ns. The operating temperature range is -55°C to 125°C, making it suitable for demanding environments.
This component is packaged in a CDIP (J) format. It offers buffered inputs and complementary outputs, with fanout capabilities of 10 LSTTL loads for standard outputs and 15 LSTTL loads for bus driver outputs. The HCT type ensures direct LSTTL input logic compatibility with specific voltage thresholds (VIL max 0.8V, VIH min 2V) and CMOS input compatibility.
Designed for applications requiring reliable data storage and transfer, the CD54HCT175F3A is a versatile building block in digital logic systems. Its high speed and wide operating temperature range make it suitable for various industrial and military applications.
| Qty | Low | High |
|---|---|---|
| 1+ | $25.52 | $25.52 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum clock frequency is 16 MHz.
The operating temperature range is -55 to 125°C.
The output current low (IOL) is 4 mA, and the output current high (IOH) is -4 mA.
The maximum supply current is 160 µA.
The propagation delay (tpd) ranges from 10 to 50 ns.
It is supplied in a CDIP (J) package.