CD54HC107F3A The Texas Instruments CD54HC107F3A is a high-speed CMOS logic dual J-K flip-flop. It features negative-edge triggering and asynchronous reset.
Mfr Part #:

CD54HC107F3A

Available from 1 distributors
Mfr Name: Texas Instruments
Texas Instruments
The Texas Instruments CD54HC107F3A is a high-speed CMOS logic dual J-K flip-flop. It features negative-edge triggering and asynchronous reset.
✓ Total Stock: 21 pcs
$ Price Range: $13.27

CD54HC107F3A Available from 1 distributor

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CD54HC107F3A Specifications Quick View

Most important parameters for selection – full specs in datasheet.
Category
Manufacturer Name
Clock Frequency
Features
Input Type
Military Grade
Number of Channels
Output Type
Supply Current

CD54HC107F3A Description

Short technical summary and product information.

The Texas Instruments CD54HC107F3A is a high-speed CMOS logic device featuring dual negative-edge triggered J-K flip-flops with asynchronous reset. This component operates within the HC technology family and supports LVTTL/CMOS input types with push-pull outputs.

 

Key electrical specifications include a maximum clock frequency of 20 MHz, a maximum supply current of 80 µA, and output current capabilities of -6 mA (IOL) and 6 mA (IOH). The device offers high noise immunity, with N IL and N IH at 30% of V CC at 5V. It operates over a wide temperature range of -55°C to 125°C.

 

Designed for improved noise immunity and increased input rise and fall times, the CD54HC107F3A includes hysteresis on its clock inputs. It also features complementary outputs and buffered inputs. The device is available in a CDIP (J) package with a package area of 130.4652 mm².

 

This flip-flop is suitable for various digital logic applications requiring reliable state storage and clocking. Its military rating and wide operating temperature range make it suitable for demanding environments.

CD54HC107F3A Quick Information

Product Type: Flip Flop
Series: CD54HC107
Canonical Name: Dual Negative-Edge Trigger J-K Flip-Flops with Reset
Subcategory: JK Flip-Flop

CD54HC107F3A Compliance

RoHS Status: RoHS Compliant
Moisture Sensitivity Level (MSL): 1 Unlimited
REACH Status: REACH Unaffected

CD54HC107F3A Estimated Pricing

Qty Low High
1+ $13.27 $13.27

Estimated market price range - modelled values for guidance only, not live distributor offers.

CD54HC107F3A Features

  • Dual negative-edge triggered J-K flip-flops
  • Asynchronous reset capability included
  • High noise immunity for reliable operation
  • Wide operating temperature range -55 to 125°C
  • Available in CDIP package

CD54HC107F3A Applications

  • Digital state storage circuits
  • Clock generation and synchronization
  • Control logic implementation
  • Sequential circuit design

CD54HC107F3A FAQs

7 frequently asked questions generated from this part’s specifications.
What is the operating voltage range of the CD54HC107F3A?

For HC types, the operating voltage range is 2V to 6V. For HCT types, the range is 4.5V to 5.5V.

What package is the CD54HC107F3A available in?

It is available in a CDIP (J) 14-pin ceramic dual-inline package.

What is the operating temperature range?

The operating temperature range is -55°C to +125°C.

What is the typical maximum clock frequency?

The typical maximum clock frequency is 60 MHz at VCC=5V, CL=15pF, TA=25°C.

What is the fanout capability?

Standard outputs can drive up to 10 LSTTL loads; bus driver outputs can drive up to 15 LSTTL loads.

What input logic compatibility does the device have?

It is compatible with CMOS and LSTTL logic; VIL max 0.8V, VIH min 2V for LSTTL.

What are the output current capabilities?

IOL (max) is -6 mA and IOH (max) is 6 mA.

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