| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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2,608 pcs
|
2608 pcs | On Request | 1 | On Request | On Request | 1133+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Clock Rate | |
| Core Processor | |
| Number of Cores | |
| Power Dissipation |
The Broadcom BCM1125HB0K800G is a highly integrated single-core MIPS64 processor based on the SB-1 architecture. It operates at a clock rate of 800 MHz and delivers 2.5 DMIPS/MHz performance. The processor includes a 32 KB instruction cache and a 32 KB data cache, along with a 256 KB shared L2 cache that is ECC protected and can be partially used as fast on-chip RAM.
The SoC integrates a DDR memory controller with a 64-bit data bus supporting up to 200 MHz clock rate (400 Mbps data rate) and compatibility with DDR SDRAM, SGRAM, and FCRAM. For high-speed I/O, it provides two 10/100/1000 Ethernet MACs compliant with 802.3, a 32-bit 33/66 MHz PCI 2.2 interface, and a HyperTransport interface running at 600 MHz with a peak bandwidth of 19.2 Gbps on an 8-bit link. The HyperTransport interface enables double-ended fabrics for linking multiple BCM1125H processors or connecting to other Broadcom processors such as the BCM1250, BCM1280, or BCM1480.
The device also includes generic I/O for boot ROM and flash, SMBus serial configuration, PCMCIA control, and two serial interfaces. Power dissipation is 4 W at 400 MHz (scales with clock frequency). The BCM1125HB0K800G is software-compatible with several other Broadcom processors and supports leading operating systems including VxWorks, Linux, NetBSD, OSE, QNX, and Teja NP OS.
MIPS64 with SB-1 architecture.
800 MHz.
32 KB L1 instruction cache, 32 KB L1 data cache, and 256 KB L2 cache.
Yes, it has two 10/100/1000 Mbps Ethernet MACs.
64-bit DDR memory controller with up to 200 MHz clock.
4 W.
RoHS3 compliant (unverified).