| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
20 pcs
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20 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Lead Style | |
| SVHC Present |
The AS7C1024A-15TJC from Alliance Semiconductor is a 128K x 8 CMOS Static Random Access Memory (SRAM) with an evolutionary pinout. This component is designed for applications requiring fast memory access.
Key electrical specifications include a minimum write cycle time of 10 ns and a maximum write cycle time of 20 ns. The address setup time is 0 ns, and the write pulse width ranges from 7 ns to 12 ns. Data valid to write end is between 5 ns and 10 ns, with a data hold time of 0 ns. The write enable to output in high Z is a maximum of 8 ns, and output active from write end is between 1 ns and 2 ns.
This SRAM is suitable for various embedded systems and data storage applications where speed and reliability are critical. Its CMOS technology ensures low power consumption during operation.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.28 | $1.28 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The write cycle time ranges from 10 ns to 20 ns over the operating range.
The write pulse width ranges from 7 ns to 12 ns over the operating range.
Chip enable (CE1 and CE2) to write end timing ranges from 8 ns to 12 ns over the operating range.
Data valid to write end timing ranges from 5 ns to 10 ns over the operating range.
The address setup time is 0 ns minimum over the operating range.
The data hold time is 0 ns minimum over the operating range.
The write recovery time is 0 ns minimum over the operating range.