ADSP-21161NKCA-100

The ADSP-21161NKCA-100 is a high-performance 32-bit floating-point digital signal processor from Analog Devices, part of the SHARC family. It features a Super Harvard Architecture with four independent buses for dual data fetch, instruction fetch, and nonintrusive zero-overhead I/O. The core operates at 100 MHz with single-cycle instruction execution, achieving 100 MIPS and up to 660 MFLOPs peak performance (440 MFLOPs sustained).

The processor supports 32-bit fixed-point, 32-bit floating-point, and 40-bit floating-point data formats. It includes a single-instruction multiple-data (SIMD) computational architecture with two 32-bit IEEE floating-point computation units, each containing a multiplier, ALU, shifter, and register file. On-chip memory consists of 128 kB (1 Mbit) of dual-ported SRAM.

The ADSP-21161NKCA-100 is supplied in a 225-ball CSP_BGA package measuring 17x17 mm and is designed for surface mount assembly. It operates from a 3.30 V supply voltage over a temperature range of 0°C to 85°C. Integrated peripherals include a host interface, link ports, and serial ports, making it suitable for audio, medical, military, wireless communications, graphics, imaging, motor control, and telephony applications.