| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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2,009 pcs
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2009 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request |
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The ADSP-21161NCCAZ100 is a high-performance 32-bit floating-point digital signal processor from the SHARC family by Analog Devices. It features a Super Harvard Architecture with four independent buses for dual data fetch, instruction fetch, and nonintrusive zero-overhead I/O. The device operates at a 100 MHz core instruction rate and delivers up to 660 MFLOPs peak and 440 MFLOPs sustained floating-point performance.
This DSP integrates a single-instruction multiple-data (SIMD) computational architecture with two 32-bit IEEE floating-point computation units, each containing a multiplier, ALU, shifter, and register file. It includes 128 kB of on-chip dual-ported SRAM, an SDRAM controller, and glueless multiprocessing support. The device supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats.
The ADSP-21161NCCAZ100 is supplied in a 225-ball CSPBGA package with a 17x17 mm footprint and surface mount mounting. It operates over a temperature range of -40°C to +105°C (TC) and requires a 3.3 V supply voltage. Interfaces include a host interface, link ports, and serial ports, with 4 serial ports, 2 link ports, and 1 SPI port available.
The ADSP-21161NCCAZ100 has a 100 MHz core instruction rate.
The operating temperature range is -40°C to +105°C (TC).
It uses a 225-ball CSPBGA package with a 17x17 mm footprint.
The supply voltage is 3.3 V.
It has 128 kB of on-chip dual-ported SRAM.
The peak floating-point performance is 660 MFLOPs.
The RoHS status is listed as RoHS3 Compliant, but this is unverified.