| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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3,022 pcs
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3022 pcs | On Request | 1 | On Request | On Request | 21+ | On Request | On Request |
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| Differential | |
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The ADCLK854 is a low jitter, low power clock fanout buffer optimized for 1.8V operation. It accepts two selectable differential inputs and supports up to 12 LVDS outputs at 1.2GHz or 24 CMOS outputs at 250MHz. Output configuration is pin programmable, allowing banks of four outputs to be set as LVDS or CMOS.
Key electrical specifications include 54 fs rms integrated jitter (12 kHz to 20 MHz), 100 fs additive broadband jitter, 2.0 ns typical propagation delay, 135 ps rise/fall time, and 70 ps output-to-output skew. Power consumption is less than 12 mW per channel at 100 MHz operation. The device also features a sleep mode for power savings.
The ADCLK854 is available in a 48-VFQFN exposed pad package (48-LFCSP-VQ 7x6.75) for surface mount assembly. It operates over the industrial temperature range of -40°C to +85°C. The device accepts a wide range of input logic levels including CML, CMOS, HSTL, LVDS, and LVPECL, making it suitable for level translation applications.
1.71V to 1.89V.
48-VFQFN Exposed Pad, CSP (48-LFCSP-VQ 7x6.75).
-40°C to +85°C.
It is listed as RoHS3 Compliant, but this is unverified.
1.2 GHz for LVDS outputs, 250 MHz for CMOS outputs.
Inputs: CML, CMOS, HSTL, LVDS, LVPECL. Outputs: CMOS, LVDS.
54 fs rms integrated jitter (12 kHz to 20 MHz).