| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
6,987 pcs
|
6987 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
2,450 pcs
|
2450 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Master fclk | |
| Mounting Type | |
| Operating Temperature | |
| Resolution (Bits) | |
| SVHC Present | |
| Supplier Device Package | |
| Tuning Word Width (Bits) | |
| Voltage |
The AD9852ASVZ is a CMOS 300 MSPS complete Direct Digital Synthesis (DDS) integrated circuit from Analog Devices. It integrates dual 12-bit D/A converters and supports FSK, BPSK, PSK, chirp, and AM modulation, making it a flexible frequency synthesis solution.
Key specifications include a 300 MHz internal clock rate, a 48-bit tuning word width, and a typical SFDR of 80 dB at 100 MHz output frequency with a ±1 MHz window. The programmable reference clock multiplier ranges from 4x to 20x, and the integrated comparator offers 3 ps rms jitter. In clock generator mode, total jitter is less than 25 ps rms.
The device operates from a 3.14 V to 3.47 V single supply and is rated for -40°C to 85°C. It is available in an 80-lead TQFP with exposed pad for surface mount assembly. Programming interfaces include a 10 MHz serial SPI-compatible port and a 100 MHz parallel 8-bit port.
The supply voltage range is 3.14 V to 3.47 V.
The operating temperature range is -40°C to 85°C.
It is available in an 80-TQFP Exposed Pad package (80-TQFP-EP, 14x14 mm).
It is listed as RoHS3 compliant in the database, though this status is unverified.
The internal clock rate is 300 MHz.
The DAC resolution is 12 bits.
The tuning word width is 48 bits.