| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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4 pcs
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4 pcs | On Request | 1 | On Request | On Request | 06+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Differential | |
| Differential Output | |
| Divider | |
| Frequency | |
| Input | |
| Mounting Type | |
| Number of Outputs | |
| Output | |
| PLL | |
| Ratio | |
| Supplier Device Package | |
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| Voltage |
The AD9517-4BCPZ is a clock generator and fanout distribution IC from Analog Devices. It integrates a low-noise phase-locked loop (PLL) with an on-chip VCO that tunes from 1.45 GHz to 1.80 GHz. The device provides 12 outputs: two pairs of LVPECL outputs operating up to 1.6 GHz, two pairs of LVDS outputs up to 800 MHz (each LVDS pair can be reconfigured as two CMOS outputs for up to 250 MHz).
Additive output jitter is 225 fs rms for LVPECL and 275 fs rms for LVDS, with channel-to-channel skew under 10 ps. The PLL accepts differential or single-ended reference inputs up to 250 MHz and includes reference monitoring and automatic switchover. The device operates from a 3.135 V to 3.465 V supply and is housed in a 48-lead LFCSP (7x7 mm) package.
Applications include low-jitter clock distribution for 10/40/100 Gb/s networking line cards, SONET, Synchronous Ethernet, and clocking high-speed ADCs, DACs, and mixers. The AD9517-4BCPZ is surface-mount and suitable for compact designs.
The supply voltage range is 3.135V to 3.465V.
It is available in a 48-VFQFN Exposed Pad, CSP (48-LFCSP-VQ 7x7) package.
It is reported as RoHS3 compliant, but this is unverified.
Yes, it includes a phase-locked loop (PLL).
It supports CMOS, LVDS, and LVPECL output logic.
The maximum LVPECL output frequency is 1.6 GHz.
Additive output jitter is 225 fs rms for LVPECL and 275 fs rms for LVDS.