| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
3,600 pcs
|
3600 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
2,560 pcs
|
2560 pcs | On Request | 1 | On Request | On Request | 1834+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Differential | |
| Divider | |
| Frequency | |
| Input | |
| Mounting Type | |
| Number of Circuits | |
| Operating Temperature | |
| Output | |
| PLL | |
| Ratio | |
| SVHC Present | |
| Supplier Device Package | |
| Type | |
| Voltage |
The AD9516-4BCPZ is a low phase noise, phase-locked loop (PLL) based clock generator and fanout distribution IC from Analog Devices. It integrates a VCO that tunes from 1.45 GHz to 1.80 GHz, providing flexible frequency synthesis. The device accepts differential or single-ended reference inputs and offers 14 outputs: 6 pairs of 1.6 GHz LVPECL outputs, 4 pairs of 800 MHz LVDS outputs (each reconfigurable as two 250 MHz CMOS outputs). Additive output jitter is 225 fs rms for LVPECL and 275 fs rms for LVDS, with channel-to-channel skew less than 10 ps on paired outputs.
The IC operates from a 3.135V to 3.465V supply and is specified over the -40°C to +85°C temperature range. It includes programmable dividers, coarse and fine phase delay adjustments, and automatic output synchronization on power-up. The device is housed in a 64-lead LFCSP (9x9 mm) surface-mount package. Typical applications include clocking for high-speed networking (10/40/100 GbE, SONET, OTU), high-speed ADCs/DACs, wireless transceivers, and ATE equipment.
The supply voltage range is 3.135V to 3.465V.
The device is available in a 64-VFQFN Exposed Pad, CSP (64-LFCSP-VQ 9x9) package.
The operating temperature range is -40°C to +85°C.
Yes, it is listed as RoHS3 Compliant, though this is unverified.
The maximum LVPECL output frequency is 1.6 GHz.
The device has a 1:14 input-to-output ratio, providing 14 outputs.
Yes, it includes a phase-locked loop (PLL).