| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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2,877 pcs
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2877 pcs | On Request | 1 | 32 | On Request | 18+ | On Request | On Request |
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The AD9515BCPZ-REEL7 is a clock fanout buffer and divider integrated circuit from Analog Devices / Maxim Integrated. It is designed for low jitter and low phase noise clock distribution, providing two independent clock outputs from a single differential 1.6 GHz maximum input.
The device includes two programmable dividers with divide ratios from 1 to 32, allowing flexible frequency division. Output 1 (OUT0) provides LVPECL levels at up to 1.6 GHz, while output 2 (OUT1) can be configured for either LVDS (up to 800 MHz) or CMOS (up to 250 MHz) levels. Additive output jitter is specified at 225 fs rms for LVPECL, 300 fs rms for LVDS, and 290 fs rms for CMOS outputs.
A time delay element with selectable full-scale values of 1.5 ns, 5 ns, and 10 ns provides 16 fine adjustment steps per range, enabling precise timing alignment. The device is configured using 4-level logic pins (S0 to S10), and phase selection provides coarse delay adjustment.
The AD9515BCPZ-REEL7 operates from a 3.3 V supply (3.135 V to 3.465 V) over a -40°C to +85°C temperature range. It is housed in a 32-lead LFCSP surface-mount package (32-LFCSP-VQ, 5 mm x 5 mm), suitable for applications such as clocking high-speed data converters, wireless transceivers, instrumentation, and broadband infrastructure.
The supply voltage range is 3.135V to 3.465V.
The component is housed in a 32-lead LFCSP-VQ (5x5) surface-mount package, also described as a 32-VFQFN exposed pad CSP.
-40°C to +85°C.
The existing database lists this part as RoHS3 compliant, but this status is unverified.
One LVPECL output (up to 1.6 GHz) and one output selectable between LVDS (up to 800 MHz) and CMOS (up to 250 MHz).
Yes, two programmable dividers with divide ratios from 1 to 32.
Yes, a delay element provides three selectable full-scale values (1.5 ns, 5 ns, 10 ns) with 16 fine adjustment steps per range.