| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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2,547 pcs
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2547 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Differential | |
| Digi | |
| Frequency | |
| Input | |
| Main Purpose | |
| Mounting Type | |
| Operating Temperature | |
| Output | |
| PLL | |
| Ratio | |
| Supplier Device Package | |
| Voltage |
The AD80052BR is a clock recovery and data retiming integrated circuit designed for STS-1 (Synchronous Transport Signal level 1) applications. It operates at a frequency of 51.84 MHz and features differential ECL (Emitter-Coupled Logic) inputs and outputs with a 1:2 input-to-output ratio. The device incorporates a phase-locked loop (PLL) for jitter attenuation and clock synthesis.
Key electrical specifications include a supply voltage range of 4.5V to 5.5V and an operating temperature range of -40°C to 85°C. The IC is housed in a 20-SOIC surface-mount package with a width of 7.50mm (0.295" pitch). The package is suitable for automated assembly and is rated for industrial temperature environments.
This component is intended for use in telecommunications and networking equipment requiring STS-1 clock recovery, such as SONET/SDH line cards, digital cross-connects, and optical network interfaces. The differential ECL interface ensures high-speed signal integrity over short distances.
The supply voltage range is 4.5V to 5.5V.
It is available in a 20-SOIC (0.295", 7.50mm Width) surface-mount package.
The operating temperature range is -40°C to 85°C.
The part is listed as RoHS3 Compliant, but this status is unverified.
The frequency is 51.84 MHz.
It uses ECL (Emitter-Coupled Logic) for both input and output.
Yes, it includes a phase-locked loop (PLL).