| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
500 pcs
|
500 pcs | On Request | 1 | On Request | On Request | On Request | On Request | 2026-06-29 21:33:16 | |
|
10 pcs
|
10 pcs | On Request | 1 | On Request | On Request | 2026-02-25 06:16:38 | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Architecture | |
| Configuration | |
| Data Interface | |
| Input Type | |
| Mounting Type | |
| Number of A | |
| Number of Bits | |
| Number of Inputs | |
| Operating Temperature | |
| Ratio | |
| Reference Type | |
| Sampling Rate (Per Second) | |
| Supplier Device Package | |
| Supplier Package | |
| Voltage |
The AD7892SQ-1 is a high-speed, low-power, 12-bit analog-to-digital converter fabricated in Analog Devices' LC2MOS process. It operates from a single +5 V supply and contains a successive approximation ADC, an on-chip track/hold amplifier, an internal +2.5 V reference, and versatile interface structures that allow both serial and parallel connection to a microprocessor.
The ADC accepts analog input ranges of ±10 V or ±5 V and features a typical conversion time of 1.47 µs with a track/hold acquisition time of 200 ns, enabling throughput rates up to 500 kSPS. Typical power dissipation is 60 mW, making it suitable for low power and portable applications.
The device is housed in a 24-lead CDIP (0.300", 7.62mm) through-hole package and operates over the full industrial temperature range of -55°C to +125°C. The flexible interface supports both parallel 12-bit data output and high-speed serial data formats for easy connection to microprocessors, microcontrollers, and digital signal processors.
The AD7892SQ-1 has a resolution of 12 bits.
The typical sampling rate is 500 kSPS.
The device operates from a single +5 V supply.
It is available in a 24-CDIP (0.300", 7.62mm) through-hole package.
The operating temperature range is -55°C to +125°C.
It supports both SPI and parallel data interfaces.
It uses a successive approximation register (SAR) architecture.