SL3S1206FUD2/HAA-VB2
NXP Semiconductors
The NXP Semiconductors SL3S1206FUD2/HAA-VB2 is a Chassis Mount Resistor. It is RoHS3 Compliant and REACH Unaffected.
| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
4 pcs
|
4 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Storage Temperature | |
| Tape & Reel |
The AD7712AN by AD is a Special Purpose ADC/DAC designed for various data acquisition applications. This component supports a 24-bit write operation to its control or calibration registers, with the A0 signal determining the data transfer destination. It can be configured for external clocking mode by setting the MODE pin low, allowing direct interface with microcontrollers and DSPs that provide synchronized serial clock output.
The read operation is also controlled by the A0 signal, which dictates whether data is accessed from the control register or the output/calibration registers. The DRDY line indicates the availability of new data in the output register, going low when data is ready and resetting high upon reading the last bit. The external clocking mode is particularly useful for systems requiring precise timing synchronization between data output and the clock signal.
This device is suitable for applications requiring precise data conversion and interfacing with digital systems. Its design facilitates integration into systems utilizing microcontrollers such as the 80C51, 87C51, 68HC11, and 68HC05, as well as most digital signal processors.
| Qty | Low | High |
|---|---|---|
| 1+ | $3.86 | $3.86 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
Data can be written to either the control register or calibration registers, always requiring 24 bits. The A0 signal determines the destination register.
The AD7712AN is configured for external clocking mode by tying the MODE pin low, making the SCLK pin an input that requires an external serial clock.
Data can be read from the output register, control register, or calibration registers. The A0 signal determines whether data is accessed from the control register or from the output/calibration registers.
The DRDY line goes low when a new data-word is available in the output data register and resets high when the last bit of data is read from the output register. It is not affected by reading from the control or calibration registers.
The RoHS status is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) is 1 Unlimited.
The REACH status is REACH Unaffected.
