| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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3,600 pcs
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3600 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The AD678BD is a complete 12-bit analog-to-digital converter (ADC) with a sampling rate of 200 kSPS. It integrates a sample-and-hold amplifier, voltage reference, clock generation, and a microprocessor-compatible bus interface in a 28-pin CDIP package. The device uses a flash architecture and provides a single-ended input with an internal reference.
Key electrical specifications include a digital supply of 5 V, typical analog supply of ±12 V, and typical power dissipation of 560 mW. Input impedance is 10 MΩ. The input voltage range supports ±10 V bipolar or 0–10 V unipolar operation, with a full power bandwidth of 1 MHz and a full linear bandwidth of 500 kHz. Signal-to-noise plus distortion is typically 72 dB.
The parallel data interface supports 8-bit or 16-bit bus widths, with right or left justification. In bipolar mode the data format is twos complement; in unipolar mode it is straight binary. The device operates from -40°C to 85°C and is available in a 28-CDIP (0.600", 15.24mm) through-hole package.
This ADC is designed for signal processing and measurement applications requiring high input impedance and direct connection to unbuffered sources. The internal reference and clock reduce external component count. Commercial, industrial, and military temperature grades are available, and MIL-STD-883 compliant versions are offered for the family.
The AD678BD has 12-bit resolution and a sampling rate of 200 kSPS.
It requires a 5 V digital supply and a typical ±12 V analog supply.
It supports ±10 V bipolar or 0–10 V unipolar input ranges.
It comes in a 28-CDIP (0.600", 15.24mm) through-hole package.
It operates over a temperature range of -40°C to 85°C.
The AD678BD is marked as RoHS3 compliant, though this has not been independently verified.
It uses a parallel data interface that supports 8-bit or 16-bit bus widths (with right or left justification).