AD6620AS

The AD6620AS is a digital receiver signal processor designed by Analog Devices. It integrates a frequency translator, fixed-coefficient decimating filters, and a programmable coefficient decimating filter. This device supports a high input sample rate of 67 MSPS for single-channel real input, 33.5 MSPS for diversity channel real input, and 33.5 MSPS for single-channel complex input.

Key features include NCO frequency translation with a worst spur better than -100 dBc and tuning resolution better than 0.02 Hz. It incorporates a 2nd order Cascaded Integrator Comb FIR filter with programmable decimation rates from 2 to 16, and a 5th order Cascaded Integrator Comb FIR filter with programmable decimation rates from 1 to 32. Additionally, a programmable decimating RAM coefficient FIR filter offers up to 134 million taps per second with 256 programmable 20-bit coefficients and decimation rates from 1 to 32.

The AD6620AS is built on a 3.3 V optimized CMOS process. It supports bidirectional synchronization circuitry for phase alignment of NCOs and synchronization of data output clocks. Outputs can be configured as serial or parallel baseband, with pin-selectable options. The serial output is compatible with SHARC, ADSP-21xx, and most other DSPs. The parallel port offers 16-bit interleaved I and Q outputs. The device includes two separate control and configuration ports and JTAG boundary scan capability.