AD608AR

The AD608AR from Analog Devices is a versatile, low-power integrated circuit designed for receiver IF subsystems. It combines a low-distortion, low-noise mixer with a complete monolithic logarithmic/limiting amplifier utilizing a successive-detection technique.

Key electrical specifications include an input bandwidth exceeding 500 MHz, a conversion gain of 24 dB, and a 1 dB compression point of -15 dBm. The device also features an 80 dB RSSI (Received Signal Strength Indicator) range and a hard-limited output. It operates from a single 2.7 V to 5.5 V supply, consuming a typical 21 mW at 3 V. Power-down mode reduces consumption to a typical 300 μW.

The mixer section is a doubly balanced Gilbert-cell mixer, operating linearly for RF inputs from -95 dBm to -15 dBm with a typical IP3 of -5 dBm. The logarithmic/limiting amplifier section handles IF frequencies up to 30 MHz. The RSSI output provides a loadable voltage from 0.2 V to 1.8 V, with phase stability of ±3° over the 80 dB range. The limiter output is a hard-limited signal at 400 mV p-p with transition times of 11 ns.

Applications for the AD608AR include PHS, GSM, TDMA, FM, or PM receivers, battery-powered instrumentation, and base station RSSI measurements. Its low power consumption and integrated functionality make it suitable for power-sensitive designs.