| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
9 pcs
|
9 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
1 pcs
|
1 pcs | On Request | 1 | On Request | On Request | 741 | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Architecture | |
| Data Interface | |
| Differential Output | |
| INL | |
| Mounting Type | |
| Number of Bits | |
| Number of D | |
| Operating Temperature | |
| Output Type | |
| Reference Type | |
| Settling Time | |
| Supplier Device Package | |
| Voltage |
AD569BD is a monolithic 16-bit digital-to-analog converter (DAC) built in Analog Devices' BiMOS II process. It uses a voltage-segmented architecture that guarantees 16-bit monotonicity over time and temperature. The chip integrates two resistor strings, selector switches, decoding logic, buffer amplifiers, and double-buffered input latches.
Key electrical specifications include typical integral nonlinearity of ±0.01% FSR and differential nonlinearity of ±0.0004% FSR. A full-scale output step settles to within ±0.001% in 3 µs typically. The reference input can be unipolar or bipolar with a nominal range of ±5 V; separate force and sense connections enable high-accuracy operation. The buffered output can deliver ±5 V into a 1 kΩ load.
The parallel interface accepts 8- and 16-bit data buses, and the double-buffered latches simplify asynchronous loading of multiple DACs. The device operates from ±10.8 V to ±13.2 V supplies and over an ambient temperature range of -25°C to 85°C. It is available in a 28-pin ceramic DIP (28-CDIP) with through-hole mounting. Typical applications include robotics, closed-loop positioning, high-resolution ADC circuits, and microprocessor-based process control.
±10.8 V to ±13.2 V.
28-CDIP (0.600", 15.24 mm) with through-hole mounting.
-25°C to 85°C.
The existing database lists it as RoHS3 compliant, but the compliance status is not independently verified.
Datasheet specifies 3 µs typical to within ±0.001% for a full-scale step; a 6 µs value is also listed in database records.
Datasheet typical INL is ±0.01% FSR.
Parallel interface compatible with 8- and 16-bit data buses.