ACEX1K

The Altera ACEX1K is a programmable logic device family offering a die-efficient, low-cost architecture. It combines a look-up table (LUT) architecture with Embedded Array Blocks (EABs). LUT-based logic provides optimized performance and efficiency for data-path, register-intensive, mathematical, or digital signal processing (DSP) designs. EABs are capable of implementing RAM, ROM, dual-port RAM, or first-in-first-out (FIFO) functions.

These elements make the ACEX 1K suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation, and microcontrollers, as required in high-performance communications applications. Based on reconfigurable CMOS SRAM elements, the ACEX 1K architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components.

The advanced process and the low voltage requirement of the 2.5-V core allow ACEX 1K devices to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches.