| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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7,844 pcs
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7844 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Differential | |
| Divider | |
| Frequency | |
| Input | |
| Mounting Type | |
| Number of Circuits | |
| Operating Temperature | |
| Output | |
| PLL | |
| Ratio | |
| Supplier Device Package | |
| Type | |
| Voltage |
The Renesas 844256DGLF is a clock/frequency synthesizer integrated circuit designed for fanout distribution applications. It incorporates a phase-locked loop (PLL) with bypass capability, accepting a crystal input and providing six LVDS outputs at frequencies up to 625 MHz. The device features a 1:6 input-to-output ratio and supports differential output signaling.
The operating supply voltage range is 3.135V to 3.465V, and it operates over a temperature range of 0°C to 70°C. The IC is housed in a surface-mount 24-TSSOP package with an exposed pad for improved thermal performance. The package dimensions are 0.173" width and 4.40mm body width.
This component is suitable for clock generation and distribution in digital systems requiring multiple low-voltage differential signaling (LVDS) clock outputs. The PLL with bypass mode allows flexible frequency synthesis and jitter cleaning. The device is RoHS3 compliant (unverified) and has an MSL rating of 1 (unlimited).
The operating voltage range is 3.135V to 3.465V.
It is available in a 24-TSSOP (0.173", 4.40mm Width) Exposed Pad package (supplier device package: 24-TSSOP-EP).
The operating temperature range is 0°C to 70°C.
It is listed as RoHS3 compliant, but this is unverified and should be confirmed with the manufacturer.
The maximum output frequency is 625 MHz.
Yes, it includes a PLL with bypass capability.
The input type is crystal, and the output type is LVDS.