| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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2,000 pcs
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2000 pcs | On Request | 1 | On Request | On Request | 1210+ | On Request | On Request |
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The 74SSTUB32865AZJBR from Texas Instruments is a 28-bit to 56-bit configurable registered buffer that supports SSTL_18 data inputs and LVCMOS switching levels. It is designed for 1.7V to 1.9V VCC operation and is a member of the Texas Instruments Widebus+ family.
This device checks parity on DIMM-independent data inputs and indicates parity errors on the PTYERR output. It supports stacked DDR2 RDIMMs, with one device per DIMM driving up to 18 SDRAM loads, or two devices per DIMM driving up to 36 loads. The pinout is optimized for DDR2 RDIMM PCB layout.
The 74SSTUB32865AZJBR operates from a differential clock and registers data at the crossing of CK going high and CK going low. All inputs are SSTL_18, except for the chip-select gate-enable (CSGateEN) and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except for the open-drain error (PTYERR) output.
Packaged in a 160-TFBGA, this component is suitable for surface mounting and operates across an industrial temperature range of -40°C to 85°C.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
1.7V to 1.9V
-40°C to 85°C
160-TFBGA
28 bits
1:2 Registered Buffer with Parity
Surface Mount
160-NFBGA (9x13)