| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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87 pcs
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87 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| Storage Temperature | |
| Tape & Reel |
The 74HCT174N is a high-speed Si-gate CMOS device featuring six edge-triggered D-type flip-flops with individual D inputs and Q outputs. It includes an asynchronous master reset input that forces all outputs LOW, independently of clock or data inputs. This device is pin-compatible with low power Schottky TTL (LSTTL).
Key electrical specifications include a typical propagation delay from clock to output (CP to Qn) of 18 ns and a maximum clock frequency of 69 MHz for HCT types. Input capacitance is typically 3.5 pF, and power dissipation capacitance per flip-flop is 17 pF.
The 74HCT174N is available in a DIP16 package and is suitable for applications requiring true outputs only and common clock and master reset inputs for all storage elements. It is specified in compliance with JEDEC standard no. 7A.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.37 | $0.37 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The package type is DIP16.
The typical propagation delay from CP to Qn is 18 ns.
The maximum clock frequency is 69 MHz.
The input capacitance is 3.5 pF.