74HC73PW,118

The NXP Semiconductors 74HC73PW,118 is a dual JK flip-flop designed for digital logic applications. It features individual J, K, clock, and reset inputs, with complementary nQ and nQ outputs. The flip-flop is negative edge-triggered, meaning state changes occur on the falling edge of the clock signal. An asynchronous reset input is also provided, which forces the nQ output LOW and nQ HIGH when active LOW.

This device operates over a wide supply voltage range of 2V to 6V and exhibits low power dissipation characteristic of CMOS technology. It boasts high noise immunity and is specified for operation across a broad temperature range of -40°C to +125°C. The clock input includes Schmitt-trigger action, making it tolerant to slower clock rise and fall times. Inputs are protected with clamp diodes, allowing the use of current-limiting resistors for interfacing with voltages exceeding VCC.

The 74HC73PW,118 is supplied in a 14-lead TSSOP package with a body width of 4.40mm. This surface-mount package is suitable for various electronic assemblies. The part offers a clock frequency of up to 83 MHz and a maximum propagation delay of 27ns at 6V with a 50pF load capacitance.