| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
2,077 pcs
|
2077 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| AEC Qualified | |
| Automotive Grade | |
| Industrial Grade | |
| Medical Grade | |
| Military Grade |
The 74HC73PW from NXP Semiconductors is a high-speed Si-gate CMOS dual JK flip-flop. It features individual J, K, clock (nCP), and asynchronous reset (nR) inputs, along with complementary nQ and nQ outputs. This device complies with JEDEC standard no. 7A and is pin compatible with Low-power Schottky TTL (LSTTL).
Key features include low-power dissipation and high tolerance to slower clock rise and fall times due to Schmitt-trigger action on the clock input. The asynchronous active LOW reset input overrides all other inputs, forcing the outputs to a defined state. The flip-flop is specified for operation over a wide temperature range of -40°C to +125°C.
This component offers significant ESD protection, exceeding 2000 V for Human Body Model (HBM) and 200 V for Machine Model (MM). It is available in multiple package options, including the 14-lead SOIC package (74HC73PW).
The 74HC73PW is suitable for various digital logic applications requiring reliable flip-flop functionality. Its design considerations include ensuring J and K inputs are stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
| Qty | Low | High |
|---|---|---|
| 1+ | $12.47 | $12.47 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The operating temperature range is -40°C to +125°C.
The 74HC73PW is a dual negative-edge triggered JK flip-flop with reset.
Yes, it has ESD protection exceeding 2000 V for HBM and 200 V for MM.
The package type is 14-SOIC.