| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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308 pcs
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308 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The 74AHC138PW,118 from NXP Semiconductors is a high-speed Si-gate CMOS 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1, and A2) and provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. The device features two active LOW enable inputs (E1, E2) and one active HIGH enable input (E3).
This decoder/demultiplexer is ideal for memory chip select decoding and can be used for demultiplexing applications. It supports a wide operating voltage range from 2V to 5.5V and operates across a temperature range of -40°C to 125°C. All inputs have Schmitt-trigger action, and the device offers balanced propagation delays.
The 74AHC138PW,118 is available in a 16-TSSOP package suitable for surface mounting. It is pin-compatible with Low power Schottky TTL (LSTTL) devices and specified in compliance with JEDEC standard No. 7A. ESD protection is provided for HBM (exceeds 2000 V) and CDM (exceeds 1000 V).
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
2V to 5.5V.
-40°C to 125°C.
16-TSSOP (0.173", 4.40mm width).
1 x 3:8 decoder/demultiplexer.
HBM exceeds 2000V, CDM exceeds 1000V.
Yes, all inputs have Schmitt-trigger action.
Surface mount.