| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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54 pcs
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54 pcs | On Request | 1 | On Request | On Request | 1997+ | On Request | On Request |
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The 7204L35P is a 4K x 9 asynchronous FIFO (First-In, First-Out) memory integrated circuit manufactured by Integrated Device Technology. This device is designed for applications requiring simultaneous read and write operations, functioning as a rate buffer in multiprocessing systems.
Key electrical specifications include a 35ns access time and a core operating voltage of 5.0V. The FIFO has a bus width of 9 bits and an organization of 4K x 9, providing a total density of 36Kb. It utilizes full and empty flags to prevent data overflow and underflow, and includes a Retransmit (RT) capability for resetting the read pointer.
The 7204L35P is supplied in a 28-lead PDIP package with a pitch of 2.54mm. The package dimensions are 36.6 x 15.24 x 3.8mm. It operates within a temperature range of 0 to 70°C. The device is RoHS3 compliant and has a Moisture Sensitivity Level (MSL) of 1.
This FIFO memory is suitable for various applications where data buffering and rate adaptation are necessary, such as in communication infrastructure or industrial automation systems.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.50 | $1.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The 7204L35P operates at a core voltage of 5.0V.
The 7204L35P is available in a 28-lead PDIP package.
The operating temperature range for the 7204L35P is 0 to 70°C.
The 7204L35P is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) for the 7204L35P is 1 Unlimited.
The 7204L35P has an access time of 35 ns.
The 7204L35P has an organization of 4K x 9.