| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
18,922 pcs
|
18922 pcs | On Request | 1 | On Request | On Request | 2020+ | On Request | On Request | |
|
1,544 pcs
|
1544 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Microchip Technology Inc. 24LCS52-I/ST is a 2 Kbit Electrically Erasable PROM (EEPROM) designed for operation across a broad voltage range from 2.2V to 5.5V. This device features a 2-wire serial interface bus compatible with I2C™ standards, operating at a maximum clock frequency of 400 kHz. It is organized as one block of 256 x 8-bit memory.
Key features include low-power CMOS technology with typical active current of 1 mA and standby current of 1 µA. The device supports software write protection for the lower 128 bytes and hardware write protection for the entire array. It also includes Schmitt Trigger inputs for noise suppression and output slope control to eliminate ground bounce. The EEPROM has a page write buffer for up to 16 bytes, offering a write cycle time of 5ms and data retention exceeding 200 years. ESD protection is rated at over 4,000V, and it boasts 1,000,000 erase/write cycles.
The 24LCS52-I/ST is available in an 8-lead TSSOP package, suitable for surface mounting. It operates within an industrial temperature range of -40°C to +85°C. This component is designed for applications requiring reliable non-volatile data storage with a small footprint and low power consumption.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.24 | $1.24 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The memory size is 2 Kbit.
The memory interface is I²C.
The maximum clock frequency is 400 kHz.
The operating voltage range is 2.2V to 5.5V.
The operating temperature range is -40°C to 85°C (TA).
It is supplied in an 8-TSSOP package.
Yes, it supports software write protection for the lower 128 bytes and hardware write protection for the entire array.