| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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4,000 pcs
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4000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| Differential | |
| Divider | |
| Frequency | |
| Input | |
| Mounting Type | |
| Number of Circuits | |
| Operating Temperature | |
| Output | |
| PLL | |
| Ratio | |
| SVHC Present | |
| Supplier Device Package | |
| Type | |
| Voltage |
The 2309-1HPGG8 is a Zero Delay Buffer integrated circuit from Renesas designed for clock distribution applications. It incorporates a Phase-Locked Loop (PLL) with bypass capability, allowing it to regenerate a clean output clock that is phase-aligned to the input reference. The device provides a 1:9 fanout, distributing a single LVTTL input to nine LVTTL outputs.
Key electrical specifications include a maximum operating frequency of 133 MHz and a supply voltage range of 3V to 3.6V. The device is non-differential for both input and output, and does not include internal dividers. It is designed for surface mount assembly in a 16-TSSOP package with a 4.40mm width.
The operating temperature range is 0°C to 70°C, making it suitable for commercial-grade applications. The part is RoHS3 compliant and has an MSL rating of 1, indicating unlimited floor life before soldering.
The maximum operating frequency is 133 MHz.
The input-to-output ratio is 1:9, meaning one input drives nine outputs.
The supply voltage range is 3V to 3.6V.
It comes in a 16-TSSOP surface mount package with a 4.40mm width.
The operating temperature range is 0°C to 70°C.
Yes, it has a PLL with bypass capability.
Both input and output logic levels are LVTTL.